Vertical field effect transistors (VFETs) are becoming viable device options for semiconductor devices, for example, complementary metal oxide semiconductor (CMOS) devices, beyond 5 nm node. VFET devices include fin channels with source/drain regions at ends of the fin channels on top and bottom sides of the fins. Current runs through the fin channels in a vertical direction (e.g., perpendicular to a substrate), for example, from a bottom source/drain region to a top source/drain region.
VFETs decouple gate length (Lg) with the device footprint. The Lg of VFETs is controlled by the gate metal height. Accordingly, variations in gate metal height lead to differences in Lg.